110 lines
4.2 KiB
Markdown
110 lines
4.2 KiB
Markdown
# [DRAFT] Specification for the _Cardiograph Architecture_
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## CPU
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### Registers
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There are four 8-bit registers:
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1. **A**, the accumulator (and the only general-purpose register)
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2. **H**, an index register for 16-bit addressing
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3. **IP**, the instruction pointer (aka program counter)
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4. **IOD**, the ID of the current I/O device
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5. **Status**
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#### Status register
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The *high byte* holds the state of the four Sense Switches. (TODO: is this easy enough to do in hardware?)
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The *low byte* holds four flags:
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- IO **E**rror
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- **N**egative
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- **Z**ero
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- **C**arry
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These are all addressed by number:*
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| S1 | S2 | S3 | S4 | | E | N | Z | C |
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|----|----|----|----|-|----|----|----|----|
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| 80 | 40 | 20 | 10 | | 08 | 04 | 02 | 01 |
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\* (Because the core instruction set doesn't include bitwise operations)
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### Instruction set
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- Instructions are two bytes long:
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one byte for the opcode, one for the operand
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- Opcode format is ```GGMM OOOO``` — **G**roup, **M**ode, **O**peration
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| | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | | 8 | 9 | A | B | C | D | E | F |
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|-------|---------|---------|---------|---------|---------|---------|---------|---------|-|-----------|-----------|-----------|-----------|-----------|-----------|----------|-----------|
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| **0** | NOP | HLT | | | | | | | | | | | | | | | |
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| **5** | LDA # | STA # | ADD # | SUB # | JMP # | SEQ # | SFL # | TGF # | | _MUL #_ | _DIV #_ | _SLT #_ | _SGT #_ | _NOT #_ | _AND #_ | _OR #_ | _XOR #_ |
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| **6** | LDA ind | STA ind | ADD ind | SUB ind | JMP ind | SEQ ind | SFL ind | TGF ind | | _MUL ind_ | _DIV ind_ | _SLT ind_ | _SGT ind_ | _NOT ind_ | _AND ind_ | _OR ind_ | _XOR ind_ |
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| **9** | DEV # | INP # | OUT # | NXT | | | | | | | | | | | | | |
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| **A** | DEV ind | INP ind | OUT ind | NXT | | | | | | | | | | | | | |
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| **F** | _RSL A_ | _RSR A_ | _ASL A_ | _ASR A_ | | | | | | | | | | | | | |
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<mark>LDH, LDH, STH, STH</mark>
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Operations in italics are extensions to the core set of operations.
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High byte reference:
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| g, m | bin | hex |
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|------|------|-----|
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| 0, 0 | 0000 | 0 |
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| 1, 1 | 0101 | 5 |
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| 1, 2 | 0110 | 6 |
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| 2, 1 | 1001 | 9 |
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| 2, 2 | 1010 | A |
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| 3, 3 | 1111 | F |
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Brief legend for mnemonics:
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- RSL/RSR: Ring Shift Left/Right
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- HLT/HGT: Jump Less/Greater Than
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- DEV: select IO device
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- NXT: "next" - move to next line / card
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TODO: format/document better:
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1. core computational operations: low nibbles of 0x, 5x, 6x
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2. arithmetic extension (optional): MUL, DIV
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3. IO extension (optional): 9x, Ax
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4. bitwise arithmetic extension (optional): NOT, AND, OR, XOR and RSL, RSR, ASL, ASR
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5. control flow extension (optional): JLT, JGT
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- The mainframe system implements at least 1, 2, and 3
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- The microprocessor trainer implements 1
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- (see note dated 2023-09-24)
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### Connections (pinout)
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<mark>TBC</mark>
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| name | in/out? | description |
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|-----------|---------|---------------|
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| RST | in | *reset* |
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| VCC | in | *power* |
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| GND | in | *ground* |
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| CLK | in | *clock* |
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| A0 - A7 | out | *address bus* |
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| D0 - D7 | out | *data bus* |
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| ABE | out | *address bus enable*: <br> low when the CPU is using the address bus |
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| DBE | out | *data bus enable*: <br> low when the CPU is using the data bus |
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| WAIT | in | *wait* — when pulled low, <br> the current operation is completed <br> and then execution pauses |
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| /RD | out | TODO |
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| /WR | out | |
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| M/IO | out | |
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### Start/Reset behaviour
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When starting up, the CPU reads the program counter from $FF.
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(Effectively executing a `JMP $FF`.)
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<mark>TODO: currently the simulator doesn't actually do this</mark> |