106 lines
4.3 KiB
Markdown
106 lines
4.3 KiB
Markdown
# [DRAFT] Specification for the _Cardiograph Architecture_
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## CPU
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### Registers
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There are four 8-bit registers:
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1. **A**, the accumulator (and the only general-purpose register)
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2. **IP**, the instruction pointer (aka program counter)
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3. **IOD**, the ID of the current I/O device
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3. **Status**
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#### Status register
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The *high byte* holds the state of the four Sense Switches. (TODO: is this easy enough to do in hardware?)
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The *low byte* holds four flags:
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**O**verflow, **N**egative, **Z**ero, and **C**arry.
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These are all addressed by number:*
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| S1 | S2 | S3 | S4 | | O | N | Z | C |
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|----|----|----|----|-|----|----|----|----|
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| 80 | 40 | 20 | 10 | | 08 | 04 | 02 | 01 |
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* (Because the core instruction set doesn't include bitwise operations)
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### Instruction set
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- Instructions are two bytes long:
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one byte for the opcode, one for the operand
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<mark>TODO: revise this based on note dated 2023-09-24</mark>
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```GGMM IIII``` - **G**roup, **M**ode, **I**nstruction
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| lo ↓ / hi → | 0 (G0, M0) | 5 (G1, M1) | 6 (G1, M2) | 9 (G2, M1) | A (G2, M2) | F (G3, M3) |
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|-------------|------------|------------|------------|------------|------------|------------|
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| **0** | END | LDA # | LDA ind | DEV # | DEV ind | |
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| **1** | NOP | STO # | STO ind | INP # | INP ind | |
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| **2** | | ADD # | ADD ind | OUT # | OUT ind | |
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| **3** | | SUB # | SUB ind | FED | FED | |
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| **4** | | JMP # | JMP ind | | | |
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| **5** | | JEQ # | JEQ ind | | | |
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| **6** | | JFL # | JFL ind | | | |
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| **7** | | FTG # | FTG ind | | | |
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| | | | | | | |
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| **8** | | MUL # | MUL ind | | | RSL A |
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| **9** | | DIV # | DIV ind | | | RSR A |
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| **A** | | JLT # | JLT # | | | ASL A |
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| **B** | | JGT # | JGT # | | | ASR A |
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| **C** | | NOT # | NOT # | | | |
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| **D** | | AND # | AND # | | | |
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| **E** | | OR # | OR # | | | |
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| **F** | | XOR # | XOR # | | | |
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TODO: assess JMPs vs. HOPs
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- RSL/RSR: Ring Shift Left/Right
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- JLT/JGT: Jump Less/Greater Than
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- DEV: select IO device
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- FED: "feed" - line feed / end of card
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TODO: format/document better:
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1. core computational operations: low nibbles of 0x, 5x, 6x
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2. arithmetic extension (optional): MUL, DIV
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3. IO extension (optional): 9x, Ax
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4. bitwise arithmetic extension (optional): NOT, AND, OR, XOR and RSL, RSR, ASL, ASR
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5. control flow extension (optional): JLT, JGT
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- The mainframe system implements at least 1, 2, and 3
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- The microprocessor trainer implements 1
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- (see note dated 2023-09-24)
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### Connections (pinout)
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<mark>TBC</mark>
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| name | in/out? | description |
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|-----------|---------|---------------|
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| RST | in | *reset* |
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| VCC | in | *power* |
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| GND | in | *ground* |
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| CLK | in | *clock* |
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| A0 - A7 | out | *address bus* |
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| D0 - D7 | out | *data bus* |
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| ABE | out | *address bus enable*: <br> low when the CPU is using the address bus |
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| DBE | out | *data bus enable*: <br> low when the CPU is using the data bus |
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| WAIT | in | *wait* — when pulled low, <br> the current operation is completed <br> and then execution pauses |
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| /RD | out | TODO |
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| /WR | out | |
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| M/IO | out | |
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### Start-up
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<mark>TODO: see if this makes sense for the mainframe </mark>
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When starting up, the CPU executes a `JMP $FF`.
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Put differently: it starts executing instructions at the address contained in `$FF`.
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<mark>TODO: currently the simulator doesn't actually do this</mark> |