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Dev notes — 2023-08-23

Problems to solve

The outline below / in the new README has some appeal, but it makes each instruction 8 bits long, which would require altering the simulator to support 8 bit addressing/storage...

Do I want to do this??

Or maybe go with the simpler "just swap NOP and FHP" plan...

→ Ok i'm going to bail on this for now; the current set is easier to work with and nicer to teach. It was good to learn about and think about this, and maybe it will come back later, but for now it feels like adding this complexity would be contrary to my goals of maximum simplicity and rapid learnability.

Instruction set layout notes

Reference: 6502

The 6502 Instruction Set Decoded

Most instructions that explicitly reference memory locations have bit patterns of the form aaabbbcc. The aaa and cc bits determine the opcode, and the bbb bits determine the addressing mode.

CHUMP reference

from David Feinberg, "A Simple and Affordable TTL Processor for the Classroom":

The CHUMP instruction set features seven key operations, each of which comes in two flavors: constant and memory. For example, there is an ADD command for adding a constant to the accumulator, and another ADD for adding a value from memory to the accumulator. The 4-bit constant portion of the instruction is ignored by the seven memory commands. Table 1 describes the seven constant commands. The corresponding memory commands operate similarly on a memory value, and have a 1 in the op-code's low-order bit.

For example, the following program increments the value in RAM location 2 repeatedly. Used properly, every READ command should be followed by a memory command, and every memory command should be preceded by a READ command.

1: 00010000 LOAD IT
2: 00100001 ADD 1
3: 01100010 STORETO 2
4: 10100000 GOTO 0

Constant instructions:

dec  bin
00   0000 Load
02   0010 Add
04   0100 Subtract
06   0110 Store To
08   1000 Read
10   1010 GOTO
12   1100 If Zero

Memory instructions (I think):

dec  bin
01   0001 Load
03   0011 Add
05   0101 Subtract
07   0111 Store To
09   1001 Read
11   1011 GOTO
13   1101 If Zero

Current Cardiograph

hex  bin
00   0000   END       *
01   0001   STO lit#
02   0010   STO addr
03   0011   LDA lit#
04   0100   LDA addr
05   0101   ADD lit#
06   0110   ADD addr
07   0111   SUB lit#
08   1000   SUB addr
09   1001   HOP lit#
0A   1010   HOP addr
0B   1011   JMP lit#
0C   1100   JMP addr
0D   1101   FTG lit#
0E   1110   FHP lit#  *
0F   1111   NOP ————  *

so the least significant bit indicates the addressing mode (0 = direct, 1 = indirect)

except for three exceptions: END, FHP, and NOP

Possible Cardiograph revisions

If NOP swaps with FHP, then a 1 in the least significant bit always indicates literal addressing:

0000   END      
0001   STO  lit#
0010   STO  addr
0011   LDA  lit#
0100   LDA  addr
0101   ADD  lit#
0110   ADD  addr
0111   SUB  lit#
1000   SUB  addr
1001   HOP  lit#
1010   HOP  addr
1011   JMP  lit#
1100   JMP  addr
1101   FTG  lit#
1110   NOP
1111   FHP  lit#

Or we could use 8 bits, and use one of the upper 4 to group instructions:

00    0000 0000  END
01    0000 0001  NOP
...   ...        NOP
0F    0000 1111  NOP

10    0001 0000  STO lit#
11    0001 0001  STO addr
12    0001 0010  LDA lit#
13    0001 0011  LDA addr
14    0001 0100  ADD lit#
15    0001 0101  ADD addr
16    0001 0110  SUB lit#
17    0001 0111  SUB addr
18    0001 1000  HOP lit#
19    0001 1001  HOP addr
1A    0001 1010  JMP lit#
1B    0001 1011  JMP addr
1C    0001 1100  FTG lit#
1D    0001 1101  FTG addr
1E    0001 1110  FHP lit#
1F    0001 1111  FHP addr

gggg iii a

g: group
i: instruction
a: addressing mode (for group 0)

makes the use of the LSB for direct/indirect addressing perfectly consistent for group 0001
makes room for indirect FTG and FHP (but those still don't seem very useful)

...

But if I want to be able to add more groups later, something like gg aa iiii might be better...

hex   bin          group  mode      op

00    0000 0000    0      --        END
01    0000 0001    0      --        NOP

50    0101 0000    1      direct    STO
51    0101 0001    1      direct    LDA
52    0101 0010    1      direct    ADD
53    0101 0011    1      direct    SUB
54    0101 0100    1      direct    HOP
55    0101 0101    1      direct    JMP
56    0101 0110    1      direct    FTG
57    0101 0111    1      direct    FHP

60    0110 0000    1      indirect  STO
61    0110 0001    1      indirect  LDA
62    0110 0010    1      indirect  ADD
63    0110 0011    1      indirect  SUB
64    0110 0100    1      indirect  HOP
65    0110 0101    1      indirect  JMP
66    0110 0110    1      indirect  FTG
67    0110 0111    1      indirect  FHP

~~let's do that!~~

(but for now i'm going to skip indirect FTG and FHP out of laziness)

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