cardiograph-computer/2023-09-25.md

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# 2023-09-25 — Dev notes
## TODO
- [x] Notes on possible architecture extensions to add support for a 16-bit IP
- [ ] add tape drive to mainframe
- review 8080 style io ports
- works bc they have 2 operands per instruction, i think
- [ ] add notes on re-arranging extended system docs
## Networking - first bits of research
- [Bus network](https://en.m.wikipedia.org/wiki/Bus_network)
- [Econet](https://en.m.wikipedia.org/wiki/Econet)
- [Telnet](https://en.wikipedia.org/wiki/Telnet)
- [Adding a serial port to my 6502 computer Mike's Software Blog](https://mike42.me/blog/2021-07-adding-a-serial-port-to-my-6502-computer)
- uxn networking — not helpful to me, i think
- https://github.com/klardotsh/uxnyap
- https://compudanzas.net/uxn_tutorial_day_7.html
- https://hacklab.nilfm.cc/xrxs/about/
## 6502 vectors
https://www.masswerk.at/6502/6502_instruction_set.html
> System Vectors
>
> $FFFA, $FFFB ... NMI (Non-Maskable Interrupt) vector, 16-bit (LB, HB)
> $FFFC, $FFFD ... RES (Reset) vector, 16-bit (LB, HB)
> $FFFE, $FFFF ... IRQ (Interrupt Request) vector, 16-bit (LB, HB)
## Increasing addressing capacity — brainstorm
Increasing the address space would require extending the IP to 16 bits. It would also mean that you would need to be able to provide a 16 bit address when JMPing.
This could add a fair amount of complexity.
Here are a few options I can think of…
### Option 1:
- Extend the IP to 16 bits
- Add an additional addressing mode for JMP instructions, which takes the high byte from the accumulator and the low byte from memory
- Advantages:
- Maybe the simplest change?
- Downsides:
- Annoying to use
- Cant easily do an indirect JMP
### Option 2:
(this is what the 6502 does, basically)
- Extend the IP to 16 bits
- Give JMP instructions two bytes of operand
- Advantages:
- Simple programming
- Disadvantages
- Variable length instruction set (probably)
### Option 3:
- Extend the IP to 16 bits
- Give JMPs two bytes of operand
- Give _all_ operations two bytes of operand, making it possible to write “LDD addr, addr”
- no i dont like this
Aside: a few instructions already have a wasted operand byte. (NOP, HLT.) Maybe a variable length instruction set isnt so bad…? → maybe this is a question to return to, when i get around to trying to build something in a logic simulator
### Option 4:
- Add a “B” register
- ? Add instruction for “Load AB”
- JMP AB
- Advantages
- Simple enough programming
- New register might be nice
- Doesnt require any ops with 2-byte operands
- Disadvantages
- Big change
- Makes the system less simple
- Need a bunch of new B reg instructions (at least 4: LDB, STB in 2 modes)
### Option 5:
- Extend IP to 16 bits
- Extend A to 16 bits
- Keep the existing instructions — they just all work on the low byte of A now
- Add new mode for LDA and STA, to r/w two bytes, with the starting addr as the operand
- Advantages
- Simple?
- All ops still just 2 bytes
- Disadvantages
- Requires new modes, which are in short supply (and/or requires making the ISA a little less tidy)
- Maybe makes arithmetic weird
### Option 6:
- this is the same as the last one but presented a bit differently
- add a B register
- add instructions for loading and storing BA as a pair
- JMP uses BA, in direct mode
- everything else (ie, arithmetic) just works on A
- advantages
- same as above
- but arithmetic isnt weird
- disadvantages
- weird
- how do you clear B?
- i guess LDA would reset B?
### Also...
- [ ] TODO: review chip 8 instruction set
- [ ] try 1802-style opcodes... or is that essentially what I already have?
## Idea: Swap Overflow flag for "IO Error"
.
## Links: 1802
- http://t2k.wdfiles.com/local--files/membership-card/RCA1802-Instruction-Set.pdf
- ** http://bitsavers.trailing-edge.com/components/rca/cosmac/MPM-201A_User_Manual_for_the_CDP1802_COSMAC_Microprocessor_1976.pdf
## Links: 6502 history
- https://www.embeddedrelated.com/showarticle/1453.php
- https://www.team6502.org/sydney-anne-holt.html
## Docs leftovers: alternative table format for instructions
| lo ↓ / hi → | 0 (G0, M0) |
|-------------|------------|
| **0** | END |
| **1** | NOP |
| **2** | |
| **3** | |
| **4** | |
| **5** | |
| **6** | |
| **7** | |
| | |
| **8** | |
| **9** | |
| **A** | |
| **B** | |
| **C** | |
| **D** | |
| **E** | |
| **F** | |
| lo ↓ / hi → | 5 (G1, M1) | 6 (G1, M2) |
|-------------|------------|------------|
| **0** | LDA # | LDA ind |
| **1** | STO # | STO ind |
| **2** | ADD # | ADD ind |
| **3** | SUB # | SUB ind |
| **4** | JMP # | JMP ind |
| **5** | JEQ # | JEQ ind |
| **6** | JFL # | JFL ind |
| **7** | FTG # | FTG ind |
| | | |
| **8** | MUL # | MUL ind |
| **9** | DIV # | DIV ind |
| **A** | JLT # | JLT # |
| **B** | JGT # | JGT # |
| **C** | NOT # | NOT # |
| **D** | AND # | AND # |
| **E** | OR # | OR # |
| **F** | XOR # | XOR # |
| lo ↓ / hi → | 9 (G2, M1) | A (G2, M2) |
|-------------|------------|------------|
| **0** | DEV # | DEV ind |
| **1** | INP # | INP ind |
| **2** | OUT # | OUT ind |
| **3** | FED | FED |
| **4** | | |
| **5** | | |
| **6** | | |
| **7** | | |
| | | |
| **8** | | |
| **9** | | |
| **A** | | |
| **B** | | |
| **C** | | |
| **D** | | |
| **E** | | |
| **F** | | |
| lo ↓ / hi → | F (G3, M3) |
|-------------|------------|
| **0** | |
| **1** | |
| **2** | |
| **3** | |
| **4** | |
| **5** | |
| **6** | |
| **7** | |
| | |
| **8** | RSL A |
| **9** | RSR A |
| **A** | ASL A |
| **B** | ASR A |
| **C** | |
| **D** | |
| **E** | |
| **F** | |