cardiograph-computer/docs/architecture-specification.md

[DRAFT] Specification for the Cardiograph Architecture

CPU

Registers

There are four 8-bit registers:

1. A, the accumulator (and the only general-purpose register)
2. IP, the instruction pointer (aka program counter)
3. IOD, the ID of the current I/O device
4. Status

Status register

The high byte holds the state of the four Sense Switches. (TODO: is this easy enough to do in hardware?)

The low byte holds four flags:
Overflow, Negative, Zero, and Carry.

These are all addressed by number:*

S1	S2	S3	S4		O	N	Z	C
80	40	20	10		08	04	02	01

• (Because the core instruction set doesn't include bitwise operations)

Instruction set

• Instructions are two bytes long: one byte for the opcode, one for the operand

TODO: revise this based on note dated 2023-09-24

GGMM IIII - Group, Mode, Instruction

lo ↓ / hi →	0 (G0, M0)	5 (G1, M1)	6 (G1, M2)	9 (G2, M1)	A (G2, M2)	F (G3, M3)
0	END	LDA #	LDA ind	DEV #	DEV ind
1	NOP	STO #	STO ind	INP #	INP ind
2		ADD #	ADD ind	OUT #	OUT ind
3		SUB #	SUB ind	FED	FED
4		JMP #	JMP ind
5		JEQ #	JEQ ind
6		JFL #	JFL ind
7		FTG #	FTG ind
8		MUL #	MUL ind			RSL A
9		DIV #	DIV ind			RSR A
A		JLT #	JLT #			ASL A
B		JGT #	JGT #			ASR A
C		NOT #	NOT #
D		AND #	AND #
E		OR #	OR #
F		XOR #	XOR #

TODO: assess JMPs vs. HOPs

• RSL/RSR: Ring Shift Left/Right
• JLT/JGT: Jump Less/Greater Than
• DEV: select IO device
• FED: "feed" - line feed / end of card

TODO: format/document better:

1. core computational operations: low nibbles of 0x, 5x, 6x
2. arithmetic extension (optional): MUL, DIV
3. IO extension (optional): 9x, Ax
4. bitwise arithmetic extension (optional): NOT, AND, OR, XOR and RSL, RSR, ASL, ASR
5. control flow extension (optional): JLT, JGT

• The mainframe system implements at least 1, 2, and 3
• The microprocessor trainer implements 1
• (see note dated 2023-09-24)

Connections (pinout)

TBC

name	in/out?	description
RST	in	reset
VCC	in	power
GND	in	ground
CLK	in	clock
A0 - A7	out	address bus
D0 - D7	out	data bus
ABE	out	address bus enable: low when the CPU is using the address bus
DBE	out	data bus enable: low when the CPU is using the data bus
WAIT	in	wait — when pulled low, the current operation is completed and then execution pauses
/RD	out	TODO
/WR	out
M/IO	out

Start-up

TODO: see if this makes sense for the mainframe

When starting up, the CPU executes a JMP $FF.

Put differently: it starts executing instructions at the address contained in $FF.

TODO: currently the simulator doesn't actually do this