cardiograph-computer/docs/architecture-specification.md

[DRAFT] Specification for the Cardiograph Architecture

CPU

Registers

There are four 8-bit registers:

1. A, the accumulator (and the only general-purpose register)
2. H, an index register for 16-bit addressing
3. IP, the instruction pointer (aka program counter)
4. IOD, the ID of the current I/O device
5. Status

Status register

The high byte holds the state of the four Sense Switches. (TODO: is this easy enough to do in hardware?)

The low byte holds four flags:

• IO Error
• Negative
• Zero
• Carry

These are all addressed by number:*

S1	S2	S3	S4		E	N	Z	C
80	40	20	10		08	04	02	01

* (Because the core instruction set doesn't include bitwise operations)

Instruction set

• Instructions are two bytes long: one byte for the opcode, one for the operand

• Opcode format is GGMM OOOO — Group, Mode, Operation

	0	1	2	3	4	5	6	7		8	9	A	B	C	D	E	F
0	NOP	HLT
5	LDA #	STA #	ADD #	SUB #	JMP #	SEQ #	SFL #	TGF #		MUL #	DIV #	SLT #	SGT #	NOT #	AND #	OR #	XOR #
6	LDA ind	STA ind	ADD ind	SUB ind	JMP ind	SEQ ind	SFL ind	TGF ind		MUL ind	DIV ind	SLT ind	SGT ind	NOT ind	AND ind	OR ind	XOR ind
9	DEV #	INP #	OUT #	NXT
A	DEV ind	INP ind	OUT ind	NXT
F	RSL A	RSR A	ASL A	ASR A

LDH, LDH, STH, STH

Operations in italics are extensions to the core set of operations.

High byte reference:

g, m	bin	hex
0, 0	0000	0
1, 1	0101	5
1, 2	0110	6
2, 1	1001	9
2, 2	1010	A
3, 3	1111	F

Brief legend for mnemonics:

• RSL/RSR: Ring Shift Left/Right
• HLT/HGT: Jump Less/Greater Than
• DEV: select IO device
• NXT: "next" - move to next line / card

TODO: format/document better:

1. core computational operations: low nibbles of 0x, 5x, 6x
2. arithmetic extension (optional): MUL, DIV
3. IO extension (optional): 9x, Ax
4. bitwise arithmetic extension (optional): NOT, AND, OR, XOR and RSL, RSR, ASL, ASR
5. control flow extension (optional): JLT, JGT

• The mainframe system implements at least 1, 2, and 3
• The microprocessor trainer implements 1
• (see note dated 2023-09-24)

Connections (pinout)

TBC

name	in/out?	description
RST	in	reset
VCC	in	power
GND	in	ground
CLK	in	clock
A0 - A7	out	address bus
D0 - D7	out	data bus
ABE	out	address bus enable: low when the CPU is using the address bus
DBE	out	data bus enable: low when the CPU is using the data bus
WAIT	in	wait — when pulled low, the current operation is completed and then execution pauses
/RD	out	TODO
/WR	out
M/IO	out

Start/Reset behaviour

When starting up, the CPU reads the program counter from $FF.
(Effectively executing a JMP $FF.)

TODO: currently the simulator doesn't actually do this