221 lines
6.8 KiB
Markdown
221 lines
6.8 KiB
Markdown
# 2023-09-25 — Dev notes
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## TODO
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- [x] Notes on possible architecture extensions to add support for a 16-bit IP
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- [ ] add tape drive to mainframe
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- review 8080 style io ports
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- works bc they have 2 operands per instruction, i think
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- [ ] add notes on re-arranging extended system docs
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## Networking - first bits of research
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- [Bus network](https://en.m.wikipedia.org/wiki/Bus_network)
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- [Econet](https://en.m.wikipedia.org/wiki/Econet)
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- [Telnet](https://en.wikipedia.org/wiki/Telnet)
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- [Adding a serial port to my 6502 computer – Mike's Software Blog](https://mike42.me/blog/2021-07-adding-a-serial-port-to-my-6502-computer)
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- uxn networking — not helpful to me, i think
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- https://github.com/klardotsh/uxnyap
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- https://compudanzas.net/uxn_tutorial_day_7.html
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- https://hacklab.nilfm.cc/xrxs/about/
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## 6502 vectors
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https://www.masswerk.at/6502/6502_instruction_set.html
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> System Vectors
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>
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> $FFFA, $FFFB ... NMI (Non-Maskable Interrupt) vector, 16-bit (LB, HB)
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> $FFFC, $FFFD ... RES (Reset) vector, 16-bit (LB, HB)
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> $FFFE, $FFFF ... IRQ (Interrupt Request) vector, 16-bit (LB, HB)
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## Increasing addressing capacity — brainstorm
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Increasing the address space would require extending the IP to 16 bits. It would also mean that you would need to be able to provide a 16 bit address when JMPing.
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This could add a fair amount of complexity.
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Here are a few options I can think of…
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### Option 1:
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- Extend the IP to 16 bits
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- Add an additional addressing mode for JMP instructions, which takes the high byte from the accumulator and the low byte from memory
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- Advantages:
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- Maybe the simplest change?
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- Downsides:
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- Annoying to use
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- Can’t easily do an indirect JMP
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### Option 2:
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(this is what the 6502 does, basically)
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- Extend the IP to 16 bits
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- Give JMP instructions two bytes of operand
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- Advantages:
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- Simple programming
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- Disadvantages
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- Variable length instruction set (probably)
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### Option 3:
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- Extend the IP to 16 bits
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- Give JMPs two bytes of operand
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- Give _all_ operations two bytes of operand, making it possible to write “LDD addr, addr”
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- no i don’t like this
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Aside: a few instructions already have a wasted operand byte. (NOP, HLT.) Maybe a variable length instruction set isn’t so bad…? → maybe this is a question to return to, when i get around to trying to build something in a logic simulator
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### Option 4:
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- Add a “B” register
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- ? Add instruction for “Load AB”
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- JMP AB
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- Advantages
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- Simple enough programming
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- New register might be nice
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- Doesn’t require any ops with 2-byte operands
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- Disadvantages
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- Big change
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- Makes the system less simple
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- Need a bunch of new B reg instructions (at least 4: LDB, STB in 2 modes)
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### Option 5:
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- Extend IP to 16 bits
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- Extend A to 16 bits
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- Keep the existing instructions — they just all work on the low byte of A now
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- Add new mode for LDA and STA, to r/w two bytes, with the starting addr as the operand
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- Advantages
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- Simple?
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- All ops still just 2 bytes
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- Disadvantages
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- Requires new modes, which are in short supply (and/or requires making the ISA a little less tidy)
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- Maybe makes arithmetic weird
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### Option 6:
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- this is the same as the last one but presented a bit differently
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- add a B register
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- add instructions for loading and storing BA as a pair
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- JMP uses BA, in direct mode
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- everything else (ie, arithmetic) just works on A
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- advantages
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- same as above
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- but arithmetic isn’t weird
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- disadvantages
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- weird
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- how do you clear B?
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- i guess LDA would reset B?
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### Also...
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- [ ] TODO: review chip 8 instruction set
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- [ ] try 1802-style opcodes... or is that essentially what I already have?
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## Idea: Swap Overflow flag for "IO Error"
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.
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## Links: 1802
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- http://t2k.wdfiles.com/local--files/membership-card/RCA1802-Instruction-Set.pdf
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- ** http://bitsavers.trailing-edge.com/components/rca/cosmac/MPM-201A_User_Manual_for_the_CDP1802_COSMAC_Microprocessor_1976.pdf
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## Links: 6502 history
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- https://www.embeddedrelated.com/showarticle/1453.php
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- https://www.team6502.org/sydney-anne-holt.html
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## Docs leftovers: alternative table format for instructions
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| lo ↓ / hi → | 0 (G0, M0) |
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|-------------|------------|
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| **0** | END |
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| **1** | NOP |
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| **2** | |
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| **3** | |
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| **4** | |
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| **5** | |
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| **6** | |
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| **7** | |
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| | |
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| **8** | |
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| **9** | |
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| **A** | |
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| **B** | |
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| **C** | |
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| **D** | |
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| **E** | |
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| **F** | |
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| lo ↓ / hi → | 5 (G1, M1) | 6 (G1, M2) |
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|-------------|------------|------------|
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| **0** | LDA # | LDA ind |
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| **1** | STO # | STO ind |
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| **2** | ADD # | ADD ind |
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| **3** | SUB # | SUB ind |
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| **4** | JMP # | JMP ind |
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| **5** | JEQ # | JEQ ind |
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| **6** | JFL # | JFL ind |
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| **7** | FTG # | FTG ind |
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| | | |
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| **8** | MUL # | MUL ind |
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| **9** | DIV # | DIV ind |
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| **A** | JLT # | JLT # |
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| **B** | JGT # | JGT # |
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| **C** | NOT # | NOT # |
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| **D** | AND # | AND # |
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| **E** | OR # | OR # |
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| **F** | XOR # | XOR # |
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| lo ↓ / hi → | 9 (G2, M1) | A (G2, M2) |
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|-------------|------------|------------|
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| **0** | DEV # | DEV ind |
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| **1** | INP # | INP ind |
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| **2** | OUT # | OUT ind |
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| **3** | FED | FED |
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| **4** | | |
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| **5** | | |
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| **6** | | |
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| **7** | | |
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| **8** | | |
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| **9** | | |
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| **A** | | |
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| **B** | | |
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| **C** | | |
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| **D** | | |
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| **E** | | |
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| **F** | | |
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| lo ↓ / hi → | F (G3, M3) |
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|-------------|------------|
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| **0** | |
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| **1** | |
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| **2** | |
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| **3** | |
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| **4** | |
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| **5** | |
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| **6** | |
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| **7** | |
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| **8** | RSL A |
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| **9** | RSR A |
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| **A** | ASL A |
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| **B** | ASR A |
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| **C** | |
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| **D** | |
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| **E** | |
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| **F** | | |