# [DRAFT] Specification for the _Cardiograph Architecture_

## CPU

### Registers

There are four 8-bit registers:

1. **A**, the accumulator (and the only general-purpose register)
2. **IP**, the instruction pointer (aka program counter)
3. **IOD**, the ID of the current I/O device
3. **Status**

#### Status register

The *high byte* holds the state of the four Sense Switches. (TODO: is this easy enough to do in hardware?)

The *low byte* holds four flags:  
**O**verflow, **N**egative, **Z**ero, and **C**arry.

These are all addressed by number:*

| S1 | S2 | S3 | S4 | |  O |  N |  Z |  C |
|----|----|----|----|-|----|----|----|----|
| 80 | 40 | 20 | 10 | | 08 | 04 | 02 | 01 |

* (Because the core instruction set doesn't include bitwise operations)

### Instruction set

- Instructions are two bytes long:
  one byte for the opcode, one for the operand

- Opcode format is ```GGMM OOOO``` — **G**roup, **M**ode, **O**peration

|       | 0         | 1         | 2         | 3       | 4       | 5       | 6       | 7       |   | 8         | 9         | A         | B         | C         | D         | E        | F         |
|-------|-----------|-----------|-----------|---------|---------|---------|---------|---------|---|-----------|-----------|-----------|-----------|-----------|-----------|----------|-----------|
| **0** | NOP       | HLT       |           |         |         |         |         |         |   |           |           |           |           |           |           |          |           |
| **5** | LDA #     | STO #     | ADD #     | SUB #   | JMP #   | JEQ #   | JFL #   | FTG #   |   | _MUL #_   | _DIV #_   | _JLT #_   | _JGT #_   | _NOT #_   | _AND #_   | _OR #_   | _XOR #_   |
| **6** | LDA ind   | STO ind   | ADD ind   | SUB ind | JMP ind | JEQ ind | JFL ind | FTG ind |   | _MUL ind_ | _DIV ind_ | _JLT ind_ | _JGT ind_ | _NOT ind_ | _AND ind_ | _OR ind_ | _XOR ind_ |
| **9** | _DEV #_   | _INP #_   | _OUT #_   | _FED_   |         |         |         |         |   |           |           |           |           |           |           |          |           |
| **A** | _DEV ind_ | _INP ind_ | _OUT ind_ | _FED_   |         |         |         |         |   |           |           |           |           |           |           |          |           |
| **F** | _RSL A_   | _RSR A_   | _ASL A_   | _ASR A_ |         |         |         |         |   |           |           |           |           |           |           |          |           |

Operations in italics are extensions to the core set of operations.

High byte reference:

| g, m | bin  | hex |
|------|------|-----|
| 0, 0 | 0000 | 0   |
| 1, 1 | 0101 | 5   |
| 1, 2 | 0110 | 6   |
| 2, 1 | 1001 | 9   |
| 2, 2 | 1010 | A   |
| 3, 3 | 1111 | F   |

TODO: assess JMPs vs. HOPs

Brief legend for mnemonics:

- RSL/RSR: Ring Shift Left/Right
- JLT/JGT: Jump Less/Greater Than
- DEV: select IO device
- FED: "feed" - line feed / end of card

TODO: format/document better:

1. core computational operations: low nibbles of 0x, 5x, 6x
2. arithmetic extension (optional): MUL, DIV
3. IO extension (optional): 9x, Ax
4. bitwise arithmetic extension (optional): NOT, AND, OR, XOR and RSL, RSR, ASL, ASR
5. control flow extension (optional): JLT, JGT

- The mainframe system implements at least 1, 2, and 3
- The microprocessor trainer implements 1
- (see note dated 2023-09-24)


### Connections (pinout)

<mark>TBC</mark>

| name      | in/out? | description   |
|-----------|---------|---------------|
| RST       | in      | *reset*       |
| VCC       | in      | *power*       |
| GND       | in      | *ground*      |
| CLK       | in      | *clock*       |
| A0 - A7   | out     | *address bus* |
| D0 - D7   | out     | *data bus*    |
| ABE       | out     | *address bus enable*: <br> low when the CPU is using the address bus |
| DBE       | out     | *data bus enable*: <br> low when the CPU is using the data bus |
| WAIT      | in      | *wait* — when pulled low, <br> the current operation is completed <br> and then execution pauses |
| /RD       | out     | TODO |
| /WR       | out     | |
| M/IO      | out     | |


### Start-up

<mark>TODO: see if this makes sense for the mainframe </mark>

When starting up, the CPU executes a `JMP $FF`.

Put differently: it starts executing instructions at the address contained in `$FF`.

<mark>TODO: currently the simulator doesn't actually do this</mark>