(notes) 2023-08-23 - Create dev note, thinking about re-arranging the ISA
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n loewen
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# Dev notes — 2023-08-23
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## Instruction set layout notes
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### Reference: 6502
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[The 6502 Instruction Set Decoded](https://llx.com/Neil/a2/opcodes.html)
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> Most instructions that explicitly reference memory locations have bit patterns of the form aaabbbcc. The aaa and cc bits determine the opcode, and the bbb bits determine the addressing mode.
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## CHUMP reference
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from David Feinberg, "A Simple and Affordable TTL Processor for the Classroom":
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> The CHUMP instruction set features seven key operations, each of which comes in two flavors: constant and memory. For example, there is an ADD command for adding a constant to the accumulator, and another ADD for adding a value from memory to the accumulator. The 4-bit constant portion of the instruction is ignored by the seven memory commands. Table 1 describes the seven constant commands. The corresponding memory commands operate similarly on a memory value, and have a 1 in the op-code's low-order bit.
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>
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> For example, the following program increments the value in RAM location 2 repeatedly. Used properly, every READ command should be followed by a memory command, and every memory command should be preceded by a READ command.
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> ```0: 10000010 READ 2
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> 1: 00010000 LOAD IT
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> 2: 00100001 ADD 1
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> 3: 01100010 STORETO 2
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> 4: 10100000 GOTO 0
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>```
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Constant instructions:
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dec bin
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00 0000 Load
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02 0010 Add
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04 0100 Subtract
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06 0110 Store To
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08 1000 Read
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10 1010 GOTO
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12 1100 If Zero
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Memory instructions (I think):
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dec bin
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01 0001 Load
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03 0011 Add
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05 0101 Subtract
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07 0111 Store To
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09 1001 Read
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11 1011 GOTO
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13 1101 If Zero
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## Current Cardiograph
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```
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hex bin
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00 0000 END *
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01 0001 STO lit#
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02 0010 STO addr
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03 0011 LDA lit#
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04 0100 LDA addr
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05 0101 ADD lit#
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06 0110 ADD addr
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07 0111 SUB lit#
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08 1000 SUB addr
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09 1001 HOP lit#
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0A 1010 HOP addr
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0B 1011 JMP lit#
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0C 1100 JMP addr
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0D 1101 FTG lit#
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0E 1110 FHP lit# *
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0F 1111 NOP ———— *
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```
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so the least significant bit indicates the addressing mode (0 = direct, 1 = indirect)
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except for three exceptions: END, FHP, and NOP
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## Possible Cardiograph revisions
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If NOP swaps with FHP, then a 1 in the least significant bit always indicates literal addressing:
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```
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0000 END
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0001 STO lit#
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0010 STO addr
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0011 LDA lit#
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0100 LDA addr
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0101 ADD lit#
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0110 ADD addr
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0111 SUB lit#
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1000 SUB addr
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1001 HOP lit#
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1010 HOP addr
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1011 JMP lit#
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1100 JMP addr
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1101 FTG lit#
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1110 NOP
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1111 FHP lit#
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```
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Or we could use 8 bits, and use one of the upper 4 to group instructions:
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```
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00 0000 0000 END
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01 0000 0001 NOP
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... ... NOP
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0F 0000 1111 NOP
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10 0001 0000 STO lit#
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11 0001 0001 STO addr
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12 0001 0010 LDA lit#
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13 0001 0011 LDA addr
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14 0001 0100 ADD lit#
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15 0001 0101 ADD addr
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16 0001 0110 SUB lit#
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17 0001 0111 SUB addr
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18 0001 1000 HOP lit#
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19 0001 1001 HOP addr
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1A 0001 1010 JMP lit#
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1B 0001 1011 JMP addr
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1C 0001 1100 FTG lit#
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1D 0001 1101 FTG addr
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1E 0001 1110 FHP lit#
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1F 0001 1111 FHP addr
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```
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```
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gggg iii a
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g: group
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i: instruction
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a: addressing mode (for group 0)
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```
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- makes the use of the LSB for direct/indirect addressing perfectly consistent for group `0001`
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- makes room for indirect `FTG` and `FHP` (but those still don't seem very useful)
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...
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But if I want to be able to add more groups later, something like `gg aa iiii` might be better...
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```
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hex bin group mode op
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00 0000 0000 0 -- END
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01 0000 0001 0 -- NOP
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50 0101 0000 1 direct STO
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51 0101 0001 1 direct LDA
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52 0101 0010 1 direct ADD
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53 0101 0011 1 direct SUB
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54 0101 0100 1 direct HOP
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55 0101 0101 1 direct JMP
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56 0101 0110 1 direct FTG
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57 0101 0111 1 direct FHP
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60 0110 0000 1 indirect STO
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61 0110 0001 1 indirect LDA
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62 0110 0010 1 indirect ADD
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63 0110 0011 1 indirect SUB
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64 0110 0100 1 indirect HOP
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65 0110 0101 1 indirect JMP
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66 0110 0110 1 indirect FTG
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67 0110 0111 1 indirect FHP
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```
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**let's do that!**
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(but for now i'm going to skip indirect FTG and FHP out of laziness)
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