n
/
cardiograph-computer
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

(readme) Update

This commit is contained in:
n loewen 2023-09-24 23:28:50 -07:00
parent ab22426a68
commit b5b1d08fe2
1 changed files with 114 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

178
readme.md
View File

@ -1,11 +1,14 @@
# Cardiograph computers
The Cardiographs are a pair of imaginary computers.
The "Cardiograph Mark I" is an educational model of a mainframe machine.
The "MicroCardiograph" is a its miniaturized descendent, a microprocessor trainer.
They use the same instruction set and have very similar CPUs.
The Cardiographs are a pair of imaginary computers:
- "Cardiograph Mark I" is an educational model of a mainframe machine
- "MicroCardiograph" is a its miniaturized descendent, a microprocessor trainer
They use the same instruction set and have very similar CPUs. (TODO: is that true?)
The main difference is in their peripheral hardware:
the Mark I is designed for batch processing programs on punched cards,
the Mark I is designed for batch processing and supports punched-card input,
while the MicroCardiograph is designed to be used interactively.
The Cardiographs were built by an imaginary enterprise, the Electronic Computer Group (ECG).
@ -18,76 +21,96 @@ There is a [simulator](micro/readme-micro.md) for the MicroCardiograph.
### Registers
There are three 8-bit registers:
There are four 8-bit registers:
1. **A**, the accumulator (and the only general-purpose register)
2. **IP**, the instruction pointer (aka program counter)
3. **IOD**, the ID of the current I/O device
3. **Status**
#### Status register
The *high byte* holds the ID number of the current **IO** device. (See the section on [IO programming](#io-programming).)
The *high byte* holds the state of the four Sense Switches. (TODO: is this easy enough to do in hardware?)
The *low byte* holds four flags:
**O**verflow, **N**egative, **Z**ero, and **C**arry.
The flags are accessed by number:
These are all addressed by number:*
| O | N | Z | C |
|---|---|---|---|
| 8 | 4 | 2 | 1 |
| S1 | S2 | S3 | S4 | | O | N | Z | C |
|----|----|----|----|-|----|----|----|----|
| 80 | 40 | 20 | 10 | | 08 | 04 | 02 | 01 |
* (Because the core instruction set doesn't include bitwise operations)
### Instruction set
- Instructions are two bytes long:
one byte for the opcode, one for the operand
<mark>TODO: revise this based on note dated 2023-09-24</mark>
```GGMM IIII``` - **G**roup, **M**ode, **I**nstruction
| lo ↓ / hi → | 0 (G0, M0) | 5 (G1, M1) | 6 (G1, M2) | 9 (G2, M1) | A (G2, M2) |
|-------------|------------|------------|------------|------------|------------|
| **0** | END | LDA # | LDA ind | DEV # | DEV ind |
| **1** | NOP | STO # | STO ind | INP # | INP ind |
| **2** | | ADD # | ADD ind | OUT # | OUT ind |
| **3** | | SUB # | SUB ind | FED | FED |
| **4** | | JMP # | JMP ind | | |
| **5** | | JEQ # | JEQ ind | | |
| **6** | | JFL # | JFL ind | | |
| **7** | | FTG # | FTG ind | | |
| | | | | | |
| **8** | | MUL # | MUL ind | | |
| **9** | | DIV # | DIV ind | | |
| **A** | | RRL # | RRL ind | | |
| **B** | | RRR # | RRR ind | | |
| **C** | | ARL # | ARL ind | | |
| **D** | | ARR # | ARR ind | | |
| **E** | | JLT # | JLT ind | | |
| **F** | | JGT # | JGT ind | | |
| lo ↓ / hi → | 0 (G0, M0) | 5 (G1, M1) | 6 (G1, M2) | 9 (G2, M1) | A (G2, M2) | F (G3, M3) |
|-------------|------------|------------|------------|------------|------------|------------|
| **0** | END | LDA # | LDA ind | DEV # | DEV ind | |
| **1** | NOP | STO # | STO ind | INP # | INP ind | |
| **2** | | ADD # | ADD ind | OUT # | OUT ind | |
| **3** | | SUB # | SUB ind | FED | FED | |
| **4** | | JMP # | JMP ind | | | |
| **5** | | JEQ # | JEQ ind | | | |
| **6** | | JFL # | JFL ind | | | |
| **7** | | FTG # | FTG ind | | | |
| | | | | | | |
| **8** | | MUL # | MUL ind | | | RSL A |
| **9** | | DIV # | DIV ind | | | RSR A |
| **A** | | JLT # | JLT # | | | ASL A |
| **B** | | JGT # | JGT # | | | ASR A |
| **C** | | NOT # | NOT # | | | |
| **D** | | AND # | AND # | | | |
| **E** | | OR # | OR # | | | |
| **F** | | XOR # | XOR # | | | |
- RRL/RRR: Ring Rotate
- JLT: Jump Less Than
TODO: assess JMPs vs. HOPs
- DEV: IO device select
- RSL/RSR: Ring Shift Left/Right
- JLT/JGT: Jump Less/Greater Than
- DEV: select IO device
- FED: "feed" - line feed / end of card
<mark>TODO: assess JMPs vs. HOPs</mark>
TODO: format/document better:
1. core computational operations: low nibbles of 0x, 5x, 6x
2. arithmetic extension (optional): MUL, DIV
3. IO extension (optional): 9x, Ax
4. bitwise arithmetic extension (optional): NOT, AND, OR, XOR and RSL, RSR, ASL, ASR
5. control flow extension (optional): JLT, JGT
- The mainframe system implements at least 1, 2, and 3
- The microprocessor trainer implements 1
- (see note dated 2023-09-24)
### Connections (pinout)
<mark>TBC</mark>
| number | name | in/out? | description |
|---------|-----------|---------|---------------|
| 1 | RST | in | *reset* |
| 2 | VCC | in | *power* |
| 3 | GND | in | *ground* |
| 4 | CLK | in | *clock* |
| 5 - 13 | A0 - A7 | out | *address bus* |
| 15 - 23 | D0 - D7 | out | *data bus* |
| 24 | ABE | out | *address bus enable*: <br> low when the CPU is using the address bus |
| 25 | DBE | out | *data bus enable*: <br> low when the CPU is using the data bus |
| 26 | WAIT | in | *wait* — when pulled low, <br> the current operation is completed <br> and then execution pauses |
| name | in/out? | description |
|-----------|---------|---------------|
| RST | in | *reset* |
| VCC | in | *power* |
| GND | in | *ground* |
| CLK | in | *clock* |
| A0 - A7 | out | *address bus* |
| D0 - D7 | out | *data bus* |
| ABE | out | *address bus enable*: <br> low when the CPU is using the address bus |
| DBE | out | *data bus enable*: <br> low when the CPU is using the data bus |
| WAIT | in | *wait* — when pulled low, <br> the current operation is completed <br> and then execution pauses |
| /RD | out | TODO |
| /WR | out | |
| M/IO | out | |
### Start-up
@ -106,15 +129,13 @@ The components of a Mark I are:
- an ECG 101 Central Processing Unit
- an ECG 102 Core Memory Unit
- an ECG 103 Card Reader
- an ECG 104 Card Punch
- an ECG 105 Line Printer
- an ECG 106 Matrix Display
Additionally, an *ECG 100 Keypunch* is used for the initial preparation of cards or tape.
- an ECG 103 Print-Key-Punch
- an ECG 104 Matrix Display
### Console
<mark>TBC TBC TBC</mark>
The console is equipped with:
- Power switch
@ -126,12 +147,13 @@ The console is equipped with:
- Memory Read Next button
- Memory Write button
- Memory Write Next button
- 16 Sense switches (<mark>TBC</mark>)
- 4 Sense Switches
- 8 Accumulator lights
- 8 Address lights
- 8 Data lights
- 8 Instruction Pointer lights (<mark>TBC</mark>)
- 4 Status Register lights
- 8 Instruction Pointer lights (<mark>review IP size?</mark>)
- 8 Status Register lights
## IO programming
@ -140,23 +162,31 @@ Only one input or output device can be accessed at a time.
### Reading data
1. Use `DEV xx` to select input device _xx_
2. Use `INP yy` to read one card into memory, beginning at address _yy_
2. Use `INP yy` to read one byte into memory at address _yy_
<mark>TODO: find a way to allow the input device to refuse to provide input</mark>
### Writing data
1. Use `DEV xx` to select output device _xx_
2. Use `OUT yy` to write one byte
3. Use `FED xx` to signal the end of a card, or the end of a line on the printer or display
2. Use `OUT yy` to write one byte from memory at address _yy_
3. Use `FED xx` to...
- card punch: load a new card
- printer: begin a new line (CR, LF)
- display: begin a new line
### Punched card format
- Cards are punched in EBCDIC
- EBCDIC data is translated into binary by the card reader/punch
FIXME:
- ~~Cards are punched in EBCDIC~~
- ~~EBCDIC data is translated into binary by the card reader/punch~~
- Only columns 1-64 are used (for a maximum of 64 bytes of data per card)
### Printer format
The printer can print up to 64 characters per line.
- The printer format is the same as the card format
- One line of printing is equivalent to one card
- The printer can print up to 64 characters per line
### Matrix display format
@ -168,11 +198,31 @@ The printer can print up to 64 characters per line.
### Device numbers
1. Input - Card Reader
2. Output - Card Punch
3. Output - Line Printer
4. Output - Matrix Display
1. card reader / typewriter
2. card punch / line printer
3. display
### Print-Key-Punch configurations
A dial allows you to select which input device to connect to the CPU:
1. none
2. card reader
3. keyboard
A similar dial selects the output device to connect:
1. none
2. card punch
3. printer
Thus, this all-in-one device allows the following configurations:
| | printer | card punch | none |
|-----------------|----------------------|------------------|--------------------------|
| **keyboard** | ***teletypewriter*** | ***auto punch*** | ***keypunch (offline)*** |
| **card reader** | (keys + print) | card duplicator | (card reader) |
| **none** | line printer | (auto punch) | (scrap metal) |
## MicroCardiograph (microprocessor trainer)